Ceramic chip scale package

Bare die such as integrated circuits may be assembled in plastic or ceramic carriers, called chip-scale packages, whose dimensions are slightly larger than the chip. CSPs are often defined as packages that are no larger than 1.5 times the area of the die or no more than 1.2 times the width or length of the die. If the carrier is a BGA type, an alternate definition is that the solder-ball pitch be less than 1 mm. The pitch of... 

Loctite 3593/ Loctite Snap-cure underfill 1 Ceramics, laminates Dispense, capillary imderfill Chip-scale packages requiring improved thermal cycling and mechanical-shock protection. 

The solder balls for area array components (e.g., ceramic ball grid arrays—CBGAs plastic ball grid arrays—PBGAs chip scale packages—CSPs) do have, of course, a processing-related cost that will not have as much effect in blurring the cost differential between lead and lead-free solders as occurs with solder pastes. Like solder bars, the cost of solder will likely track more closely with the raw material cost. 

The most advanced implementation of cofired-ceramic-packaging technology is the thermal conduction module (TCM) used in large-scale computers (IBM) (4, 72, 74). This package can accommodate over 100 flip-chip-bonded ICs on a 90 by 90 mm cofired ceramic substrate. The multilayer ceramic substrate contains 33 metal layers for chip pad redistribution, signal interconnection, and power distribution (Figure 14). Each chip contains 120 bonding pads, and 1800 pins are brazed to the bottom of the substrate for connection to a PWB. 

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