California at Irvines VSS

The University of California at Irvine s YHDL Synthesis System (VSS) produces Register Transfer level designs, which can then passed on to the Microarchitecture and Logic Optimizer (MILO) system for optimization and library binding. The VSS includes transformations, scheduling, data path synthesis, and functional synthesis. 

VHDL behavioral and dataflow descriptions at the logic. Register Transfer, and algorithmic levels. Signals can be typed, can have a specified bit width, and can have clocking and sensitivity information specified. 

Uses a hierarchical control/data flowgraph , with nodes representing READs, WRITEs, and operators, and nets representing connectivity and signal attributes. A graphical display allows the user to view this flowgraph. 

Uses cleanup rules to eliminate redundant operations in the flowgraph, and optimization rules to replace behavioral constructs with others more closely matching library components. Also uses transformation for loop unwinding and loop pipelining. 

uses percolation scheduling to allow data-independent operations to percolate toward earlier control steps, not considering resource constraints. To meet resource constraints, the mobility of each operation in the control step is computed, and operations with higher mobility are delayed until later control steps. 

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