Bitstream fault injection

FPGA Memory Configuration Bitstream Fault Injection... 

Configuration Bitstream Fault Injection Experimental Results... 

Table 6.1 summarizes the bitstream fault injection campaign. As one can see, 48,323 errors affected the DUT, and only 808 faults (1.6%) were not detected by the proposed hardening approach, achieving an overall fault detection coverage of 98.4%. 

This book exposes the reasons behind the concerns surroimding a system s fault tolerance. Some of the most irrrportarrt farrlt tolerance techniques presented in the literature are analyzed arrd three novel hybrid techniques to detect farrlts in processors are presented in detail. It also covers fault injection techniques appUed to the novel techrriques, including farrlt injection by simrrlation, configuration bitstream farrlt injection, and neutron arrd Cobalt-60 beams irradiation experimerrts. 

The book is organized as follows Chap. 2 presents the terminology and general concepts used in this work. Chapter 3 describes existing fault tolerant techniques for processors presented in the literature. Chapter 4 describes the fault tolerant techniques implemented in this work to detect transierrt fairlts in processors, from which two are known software-based and three are new lybrid techniques. Chapter 5 presents experimental fault injection campaigns for the implemented fairlt tolerarrt techniques. Chapter 6 presents the configuration bitstream fairlt injection campaign and results. Chapter 7 presents radiation experiments on some of the proposed techniques. Chapter 8 describes future work and concludes the book. 

Soft errors can be detected and corrected by the system s logic, meaning that it does not require a hard reset to recover from an error. Sections 7.1.2 and 7.2.2 present neutron irradiation experiments simulating the effect of SEE in Flash-base and SRAM-based FPGAs, while Chaps. 5 and 6 present fault injection simulation experiments simulating SEEs at RTL level and in the configuration memoiy bitstream, respectively. In this work, SEUs and SETs will be used to describe transient faults that the proposed techniques can cope with. 

Although the effect of faults is increasing, the rate is not yet sufficient to test fault tolerant techniques at ground level. In order to do so, fault emulation and testing is necessary. In this Section, we will go over a few options to do so, such a software fault injection by simulation, fault injection in the FPGA s memory configuration bitstream and irradiation experiments. 

---