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Approaches to defect characterization, mitigation, and reduction

IBM Semiconductor Research Development Center, NY, USA Now at Advanced Technology Development, GLOBALFOUNDRIES, NY, USA [Pg.433]

Flgnre VI3 Cu CMP process. Copper, barrier metals (e.g., Ta/TaN or Co), cap or hardmask (e.g., TiN, TEOS oxide, nitride, or SiCOH), and interlevel dielectric (e.g., low-k SiCOH) are all removed to complete the definition of one level of Cu interconnects. [Pg.435]

In this chapter, the term CMP-related defects is utilized to capture all the defects originated from, attributed to, and modulated by CMP. They are categorized by their source and formation mechanism in the following sections. The roles of consumables in defect generation will be elucidated as well. [Pg.435]

Both foreign materials (FM) and polish residues (PR) are additive defects residing on the wafer surface as a result of a manufacturing process. As the names suggest, FM usually refers to unwanted material after CMP, while PR relates to the debris and residues resulting from polishing. The two terms are usually used interchangeably. [Pg.436]

Caution must be taken to monitor the area within a few millimeters from the wafer edge as it is the potential source of FM and PR defects. The edge of the wafer presents itself as the boundary where the thin film layers discontinue. Adhesion loss can occur [Pg.437]


See other pages where Approaches to defect characterization, mitigation, and reduction is mentioned: [Pg.433]    [Pg.437]    [Pg.439]    [Pg.441]    [Pg.443]    [Pg.445]    [Pg.447]    [Pg.449]    [Pg.451]    [Pg.453]    [Pg.455]    [Pg.457]    [Pg.459]    [Pg.461]    [Pg.433]    [Pg.437]    [Pg.439]    [Pg.441]    [Pg.443]    [Pg.445]    [Pg.447]    [Pg.449]    [Pg.451]    [Pg.453]    [Pg.455]    [Pg.457]    [Pg.459]    [Pg.461]    [Pg.458]   


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Defect characterization

Mitigation

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