A Cost Comparison of VLSI Integration Schemes

Institute of Microelectronics, Tsinghua University Beijing 100084, P. R. China, dengyd tsinghua.edu.cn 

Electrical and Computer Engineering Carnegie Mellon University 5000 Forbes Avenue, Pittsburgh, PA 15213-3891 USA, maly ece.cmu.edu 

Abstract Besides the dominant monolithic VLSI integration paradigm, many non-monolithic schemes have already been developed in the past. Typical such schemes include wafer scale integration or multi-reticle wafer, multi-chip module, and 3-D integration. In this chapter we compared these different schemes in a unified cost analysis framework. Our model takes a few parameters extracted from representative fabrication and evaluates the cost efficiency. Our analysis proves that the proposed 2.5-D out significantly outperform other integration paradigms from a cost perspective. 

Keywords 2.5-D integration, monolithic VLSI integration, multi-reticle wafer, multi-chip module, 3-D integration, yield, silicon area, fault coverage. 

In this chapter, we first briefly review the concepts of major non-monolithic integration approaches. Then we describe an analytical cost analysis framework and then apply it to compare all 5 integration styles discussed before. 

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Cost Analysis First, we are going to establish a unified cost analysis framework to compare the fabrication cost of different integration schemes. In fact, given a VLSI application, there are many different ways to build it on silicon. Accordingly, the first research objective is to provide an apple-to-apple cost comparison for different integration styles. 

Finally, we pick up the cost optimum of each VLSI integration schemes discussed above and compare them in Fig. 2.5. To make a clearer comparison, we normalize the costs of different integration styles to that of the monolithic System-on-chip. 

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