VHDL vs. Verilog The Language Issue

VHDL is a case insensitive language while Verilog is a case sensitive language. 

by definition, requires that all the different values of an expression in a case statement be covered. However, this is not required in Verilog. If the user knows that all possible values of the case expression have been covered, one should use the Synopsys synthesis full case pragma. This prevents latches from being inferred due to not assigning values to a reg/signal under all possible conditions. 

Example 2.5 Verilog Code Using Negative Numbers 

In Example 2.S, A will be assigned the value 1001 which is the 2 s complement of -7, but interpreted as +9 in the expression A + C. One way to get around this is shown below. 

In VHDL, a component declaration is required before instantiating a component. This defines the template of the component being instantiated and includes information such as, port mode or direction, port names and the data type of the ports. These templates or component declarations are bound to sub-design entities using configuration declaration statements. Hence, when reading in a VHDL netlist you 

---