Small Designs Synthesize Faster

Experimental studies have shown that logic circuits of size between 2000 to 5000 gates are best handled by a logic optimizer. This implies that in a Verilog HDL model, always statements must not be inordinately long. A design should be structured into multiple always statements or multiple modules. 

There is no correlation between the gates produced and the number of lines of Verilog HDL code. A 2500-gate circuit could have been synthesized from a 10-line Verilog HDL code (may have a for-loop and/or vectors) or from 10,000 lines of Verilog HDL code (maybe from a large case statement with simple assignments). 

Synthesis run-times, mainly logic optimization, are exponential with design size. Thus it is critical to keep the sizes of sub-blocks within a design manageable. 

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The information presented above suggests that the design of zeolite pore structures is feasible if pure-silica syntheses are used with water-soluble organics that do not decompose at syndiesis conditions diat may last for several months. For most practical cases, faster synthesis times and the addition of heteroatoms, e.g. Al, are desired. Small amounts of alkali-metal cations and heteroatoms will most likely be acceptable. However, large amounts of alkali-metal ions and heteroatoms will alter the reaction chemistry sufficiently to override or modify the structure-directing effects of the organic species. 

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