Single instruction multiple data streams SIMD

SISD single instruction, single data stream SIMD single instruction, multiple data stream MIMD multiple instruction, multiple data stream. 

Single instruction stream, multiple data stream (SIMD). Each processor operates in lock step, with an identical instruction stream but different data streams. 

During the early part of this decade, there was a vivid debate between proponents of MIMD (multiple instruction stream, multiple data stream) and SIMD (single instruction stream, multiple data stream) type parallel computers. This taxonomy, which stem from Flynn s classification [25,26] of possible computer architectures, can now be said to be mostly of historical and academic interest. 

SIMD. This Single instruction stream, multiple data stream or SIMD family employs many fine- to medium-grain arithmetic/logic units (more than tens of thousands), each associated with a given memory block (e.g., Maspar-2, TMC CM-5). Under the management of a single system-wide controller, all units perform the same operation on their independent data each cycle. 

More limited versions of SIMD architectures are common today. Rather than simultaneously computing all results as is done in the CM-2, the more modern SIMD architectures pipeline data through one or more execution units and can achieve high computational rates due to the repetitiveness of the work involved. This arrangement is used in vector processors (for example, the Cray XI ). Also, modern microprocessors now have extensions allowing single instructions to perform identical operations on multiple pieces of data. Examples include Intel s Streaming SIMD Extensions (SSE) and Motorola AltiVec used in recent versions of the IBM POWER processor. 

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