Bistable latch

This is called restoring logic. However, the NanoCell as a whole has some resistance, so this is not possible without some outside influence. One such method is to use a bistable latch or Goto pair at each output pin for restoring logic.Consider the very simple circuit displayed in Figure 6.10. 

Figure 6.10 This is a bistable latch consisting of metal-NDR-metal-NDR-ground with a capacitor in series with the ground NDR. When Vbias is high, there are two stable states 0" and 1". The state is determined by current flowing into the data node.

The next question is. In which of the two states will the bistable latch reside, and what are the determinants To set the latch, Vbias is brought to a low voltage, such that the latch is now in a monostable state as in Figures 6.11a and... 

Figure 6.12 Figures (a) and (b) demonstrate currents that cause the bistable latch to flip before it is clocked. Current must stay within an acceptable range Umj. - Imji) to prevent this phenomenon.

Figure 6.14 This is a NanoCell whose output pin is connected to a bistable latch.

Scoring a voltage in - voltage out NanoCell with bistable latches is very different. Recall that for a latched output there are only two possible output voltages. Therefore, if there are n different outputs then there are only 2" possible output graphs and the problem is now a discrete optimization... 

Figure 6.31 On the left, the output voltage of an XOR gate is shown. Note that due to the bistable latch, there are just two possible output voltages. Output current is shown on the right.

Recall that with the voltage in - voltage out model, the output pins are connected to bistable latches. A potential architecture that includes this feature is displayed in Figure 6.37. 

Figure 6.37 This is an architecture that includes bistable latches. The side view demonstrates the bistable latch outside the NanoCell. The figures on the right illustrate a potential process for constructing such a NanoCell.

Figure 6.38 This is a 20 pin NanoCell trained as an XOR gate. Pins A and B are set to input, and pin Out is set to output. Input voltages and output current and voltage are shown. The dotted line is the clock voltage for the bistable latch.

Another potential problem with bistable latches is current drain through input pins. This can make the bistable latches on output pins less effective. This problem is easily solved by allowing no molecules to be directed into an input pin. Hence, it is not possible for current to flow in this direction. 

The point of using a voltage in - voltage out model with bistable latches for restoring logic is to eventually hook multiple NanoCells together to work in unison. This has been a very difficult problem and we are still trying to... 

The issue of hooking NanoCells has proved difficult so far. As mentioned previously, the bistable latches can be fairly unstable. They tend to work for only very small ranges of input voltages and current drain can cause... 

In previous sections, NanoCell training proofs were presented. In this section, some possible methods for improving these results are explored. First, the results are for voltage in - current out NanoCells, and NanoCells will actually be voltage out. Therefore, the results should be adapted to this case. This will be extremely simple if the voltage in - current out observations hold for voltage in - voltage out with the new bistable latches. 

There are still many substantial obstacles to overcome. Large circuits of simulated NanoCells working in concert must be obtained. This achievement should be realized shortly, however. In addition, results seen in simulation should be validated by tests on physical NanoCells. Simulations should be adapted to reflect what is seen in these experimental cells. After obtaining working physical NanoCells, the issues of size and power must be addressed. What kind of size advantage is possible with a NanoCell What kind of power is required to run a chip of many thousands of the cells Here bistable latches may prove a liability as they draw constant current. 

Several FLC projects have also been based on C2 (JOERS/Alvey, Thorn/CRL, Sharp). The fact that bistable switching only takes place through being latched by the chevron surface is compensated for by a number of advantages. First of all, the surface alignment is relatively simple, as the outer surfaces do not switch but only work togeth-... 

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