Silicon dioxide etching

Figure 9. Dependence of silicon and silicon dioxide etch rates on the percentage of Hz in CF4-H2 plasmas, (seem is standard cubic centimeters per minute.) (Reproduced with permission from reference 118. Copyright 1979 The Electrochemical Society, Inc.)...

Figure 5.16 Novel fabrication process for the third generation of micromachined electrospray emitter tips silicon support wafer (blue), 200 nm thick silicon dioxide etch-release layer (white) which is patterned using a HF-based wet-etch step, single polySi micro-nib layer (red) housing the reservoir and the nib tip which is defined using either a chlorine- or an SF6-based dry etch and single UV photolithographic masking step (black).

The Flamm formulas lead to the expression for the silicon-to-silicon dioxide etching selectivity ... 

The SiC Schottky diodes and capacitors that have been processed by the authors were processed on either 6H or 4H substrates (n-type, about 1 x 10 cm ) with a 5-10- m n-type epilayer (2-6 x lO cm" ) [123, 124]. A thermal oxide was grown and holes were etched for the metal contacts. In the case of the Schottky sensors, the SiC surface was exposed to ozone for 10 minutes before deposition of the contact metal. This ozone treatment produces a native silicon dioxide of 10 1 A, as measured by ellipsometry [74, 75]. The MISiC-FET sensors (Figure 2.9) were processed on 4H-SiC, as previously described [125]. The catalytic metal contacts consisted of 10-nm TaSiyiOO-nm Pt, porous Pt, or porous Ir deposited by sputtering or by e-gun. 

A representative sample of terpolymers was exposed to a variety of etchants for polysilicon and silicon dioxide, and the results are given in Table V. The ratio of the etch rate of the substrate to the etch rate of the resist must be at least 2 1 for the resist to be a viable etch mask. Inspection of Table V, shows that the materials examined are unacceptable for only the QFj — CF3CI (4 1) plasma. The etch rates are comparable to those for PMMA the a-keto-oxime exhibits essentially no effect on that rate and the nitrile affords a slight decrease in the plasma etch rate. The etch rates of some commercially available materials are shown for comparison. 

Silicon Dioxide and Silicon Nitride. Silicon dioxide can also be etched by F atoms in a downstream discharge configuration. However, because of the strength of the Si-O bond, etch rates (equation 29) are low without particle bombardment (95). 

A number of other types of processes that can be considered a form of self-assembly at surfaces are just beginning to appear. The selective oxidation of silicon, followed by etching of the silicon dioxide, as a route to silicon nanowires is an example172 the galvanic deposition of platinum on selenium nanostructures, followed by removal of the selenium, to make nanowalls with complex shapes is a second173,174. 

The wafers were coated with silicon dioxide (400 nm thickness) and silicon nitride by low pressure chemical vapor deposition (LPCVD) alternately. The chips were fabricated by photolithography and etching. The catalyst (for the application Pt) was introduced as a wire (150 pm thickness), which was heated resistively for igniting the reaction. The ignition of the reaction occurred at 100 °C and complete conversion was achieved at a stochiometric ratio of the reacting species generating a thermal power of 72 W (Figure 2.28). 

The rapid mixer is composed of layers that are fabricated separately and then assembled together. The main four channel device, represented by the cartoon of Fig. 12.2, is etched through a 1-mm-thick silicon wafer using an anisotropic Bosch process RIE (Unaxis 770, Unaxis). The depth of this etch requires a thick mask. We use a 7 pm layer of PECVD silicon dioxide (GCI PECVD Group Sciences Incorporated, San Jose, CA). This mixer is sandwiched between two 100 pm thick poly(dimethylsiloxane) (PDMS) layers (Duffy et al, 1998), which contain channels in a T configuration. 

A silicon dioxide layer 3 is formed on an insulating CdTe substrate 1. A photo-resist coating 5 is formed over the silicon dioxide layer. The photo-resist layer is patterned and the silicon layer is partly etched away. The photo-resist layer is removed and a film of HgCdTe 9 of a first mercury to cadmium ratio is deposited by liquid phase epitaxial deposition over the entire surface of the substrate. The HgCdTe film is only formed at regions where the CdTe substrate is exposed and does not adhere to the silicon dioxide. Next, the silicon dioxide layer is removed. In order to increase the window of frequency response of the detectors, the process is repeated using a second mercury to cadmium ratio different from the first ratio. 

A p-type layer 18 and an n-type layer 20 of HgCdTe are grown epitaxially on a substrate 52 of cadmium zinc tellurium. A set of through holes are formed which extend through the layers 18 and 20 up to the surface of the substrate. A silicon dioxide layer is applied and at each detector a window is etched. A contact metal 24A is applied within each window. Contacts 24 and 26 are constructed on the detectors and on the read-out chip 14. The chip and the substrate 52 are pushed together to compress the contacts 24 and 26 against each other which cold welds them to each other. 

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