Sigma-delta ADC

Sigma-delta ADCs are not a universal panacea, as they still only acquire data no faster than 200 kHz. Although this appears to be fast, both the interferogram and the laser signal have to be oversampled by as much as an order of magnitude. Hence the actual digitization rate is equivalent to only 20 kHz for a sample-and-hold ADC. At the present time this limits the use of these high-bit ADCs to slower data acquisition rates. 

Obviously, this problem would be alleviated if ADCs of higher dynamic range were used. Although 18-bit ADCs are commercially available, they are typically slower and more expensive than their 16-bit counterparts. A relatively recent development has been the introduction of the sigma-delta ADCs (see Section 3.4). These devices have an effective dynamic range of about 21 bits but sample the signals from the infrared and laser detectors simultaneously at equal intervals of time rather... 

Fig. 10 Simplified overview of the functional blocks of a sigma-delta ADC...

Modulation-based readout circuits have gained popularity for interfacing with capacitive and inductive MEMS sensors to reduce the noise levels of l// noise and direct current (dc) offset in the circuit. Modulation-based circuits are based on sigma-delta (2A) converter [56,62,65], successive approximation register (SAR) analog-to-digital converter (ADC) [56,66], chopper modulation [54,55,58], pulse-width modulation (PWM) [57,61,63], and frequency modulation (FM) configurations [42,48,51,64,68],... 

The significant types of ADC are flash-type converter, successive approximation-type, counter-type, sigma-delta converter, and integrating-type ADC. The sigma-delta converter and the integrating type ADC offer more accuracy and noise reduction than any other type ADCs, but they are very slow. The flash converter is the fastest of all... 

The three most common ADC architectures are known as the successive approximation, ramp/counter, and sigma-delta, but there are a plethora of others. In addition, the overall device can use two or more methods in series - pipelined . Selection of the ADC architecture is driven by ROIC resources such as power, ADC location, and available real estate, as well as system performance needs such as bit resolution and linearity. 

Harris, 1990] Harris, S. (1990). The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta-Sigma ADCs. J. Audio Eng. Soc., 38(7/8) 537-542. 

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