Self-aligned gate process

With a view to improving device performance, Kirwan and co-workers proposed the polysilicon self-aligned gate process in 1969. This process not only improved device reliability, it also reduced parasitic capacitances. Furthermore, in 1969, the metal-organic chemical vapor deposition (MOCVD) process was developed hy Manasevit and Simpson, which found widespread adoption in the fabrication of compound semiconductors such as GaAs. 

Fig. 22 Schematic cross section created by the RIE process (a) and the result of the subsequent gold evaporation (b) for the preparation of self aligned gate contacts...

Fig. 23 SEM images of a short-channel structures with self aligned gate contact prepared by RIE process the gate is situated in the trench between the source and drain contacts. Right hand side figure taken from [42]...

Although transparent substrates allow the use of a self-aligned process (Asama et al 1983), it is difficult to work with gate lengths below 5 fim, especially in large-area devices. Thus L is essentially a fixed number and W is adjusted to satisfy the electrical requirements in the ON state. 

Fig. 5.12. A schematic showing the self-aligned process flow implemented in the parylene encapsulation process. An extra exposure step and mask is required to fill in interconnect shadowed by the gate layer, but these exposures are performed on the same photoresist and the total number of layers remains the same.

In this fabrication flow, the gate electrode is used as a mask for back side exposing light. This method is referred to as a self aligned method and it has been widely investigated as a way to reduce number of masks needed in photolithographic processes. 

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