RTL Simulation

High level, hierarchical models provide useful analysis of different types of memory structures within the processor. Flows through the models and utilization parameters can be determined for different structures. Low level, register transfer level (RTL) simulation of specific structures usually give a more accurate picture... 

Soft errors can be detected and corrected by the system s logic, meaning that it does not require a hard reset to recover from an error. Sections 7.1.2 and 7.2.2 present neutron irradiation experiments simulating the effect of SEE in Flash-base and SRAM-based FPGAs, while Chaps. 5 and 6 present fault injection simulation experiments simulating SEEs at RTL level and in the configuration memoiy bitstream, respectively. In this work, SEUs and SETs will be used to describe transient faults that the proposed techniques can cope with. 

XC4000 devices have dedicated resources for a Global Set/Reset net that can be utilized to initialize all the sequential elements inside the CLBs and lOBs on the device. This capability can be used, if your design has a global signal that effects every flop in your design, by instantiating a STARTUP component from the Xilinx library. However, to simulate the asynchronous behavior in the RTL code you must include the asynchronous capability in the code and later disconnect the asynchronous net and instead cormect it to the STARTUP component. 

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