Pixel capacitance

For example, in a typical SXGA (1280 x 1024) AMLCD, the refresh rate is 60 Hz, the frame time is 16.7 msec, and the line time is 16.3 psec. For 6-bit resolution, the RC charging time constant must be less than 3.3 psec. The total pixel capacitance is about 0.5 pF, so the TFT on-resistance must be less than 6.6 Mil. From liquation... 

In 3-a-Si H TFTs 200 dpi AM-PLED the active-resistor had a channel width of 15 pm, and the driving and switching TFTs had channel widths of 105 and 30 pm, respectively, with the same channel length of 10 pm. The storage capacitance was 0.4 pF. The top and cross-section views of the AM-PLED backplane are shown in Figure 9.5. The inset shows a blow up of single pixel electrode circuit and its cross-section view. 

Fig. 4.11. Optical images of a printed polymer TFT array at increasing magnification, showing the whole 128 x 128 array (a), small regions of the array (b), and a single device (c). Note the printed semiconductor confined to the channel region in (b) and (c). (d) Equivalent circuit for the pixel, showing the gate and data address lines, the TFT and different capacitances. In the...

The design of active-matrix TFT (AM-TFT) backplanes for capacitive media, such as electrophoretic ink, has been extensively reviewed [1] and we discuss here some of the most relevant issues for printed backplanes. A simplified equivalent circuit for a pixel in an AM-TFT backplane is shown in Fig. 11.14. 

The pixel layout was optimized with respect to the storage capacitance (CSt), parasitic capacitance (Cp) and transistor dimensions. The goal was to achieve short... 

Fig. 14.7. Equivalent circuit of one pixel. The source, drain, and gate of the TFTs are indicated by S, D, and C, respectively. The storage capacitor is indicated by Cst, the pixel capacitor by CEmk> arid the parasitic gate-drain capacitance by Cgc. ...

Fig. 4. (Left) Schematic representation of an active matrix LCD display, showing single transistors driving capacitive pixel elements. (Right) OLED displays, on the other hand, require current-based driving, and therefore, multi-transistor pixel architectures are more common.

The primary requirements of the pixel circuit are that the liquid crystal capacitor charges fully during the time that each row is addressed and holds the charge for the time between refreshing the display. Consider the example of a 25 x 25 cm panel of 500 x 500 pixels. Each pixel has an area of 500 pm and a capacitance of roughly 10 pF. The panel is refreshed at the usual video rate of 30 Hz, so that each row is addressed for 60 ps (30 ms/500). Each TFT must deliver a charge of 10" C in 60 ps, in order to charge the pixel up to 10 V, which corresponds to a current of 1.5 pA. The TFT transfer characteristics in... 

In both the liquid crystal and scanner a-Si H arrays, the time limitation of the circuit is not the intrinsic switching speed of the TFT, but is the RC time constant of the pixel circuit, comprising the capacitance of the sensor and the resistance of the TFT. Complete... 

Fig. 15. Pixel circuit considering parasitic capacitances and substrate cap>acitances. The size of switching and driving TFT is 22/5 /an and 200/5 jMH, respectively. Node A means the floating gate electrode of the driving TFT.

Very wide dynamic range. Usually a transfer characteristic curve (input-to-output) with a slope ( ) of 1 is ideal. However, a capability to alter this slope electronically can be advantageous when very high dynamic reserves are necessary with pixels of limited capacitance. 

Fig. 4.19 Demonstration of fast in switching for a polymer LED pixel. In this figure a LED was fabricated on a strip-line configuration to minimize the stray input capacitance.

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