NMOS transistor operation

The operation of the NMOS transistor shown schematically in Figure 12 can be considered in the light of the previous discussion of a MOS capacitor. When no voltage is applied to the gate, the source and drain electrodes correspond to p-n junctions connected through the p region therefore only a small reverse current can flow from source to drain. On the... 

Fig. 6.1. A schematic showing the structure and regions of operation of a NMOS c-Si FET. The voltages shown are for illustration only. When Vas exceeds the threshold voltage and Vds is small the channel is inverted at both sides with approximately the same Q and the device behaves as a resistor. When a substantial Vns is applied, the field induced by the gate is partially canceled on the drain end. When the potential at the drain end drops below Vr, Q 0 and the carrier velocity increases to compensate, which leads to pinch-off and a saturation of the transistor characteristic. The carriers are all physically located very close to the gate dielectric interface, the triangle is illustrating that the carrier density is not constant. Since the current flow is constant across the length of the channel, the velocity and lateral field in saturation are not uniform.

A possible fabrication process flow for a single 90-nm technology node microprocessor CMOS inverter, consisting of two transistors— nMOS and pMOS—is presented in this section. Cross-sectional views of the inverter are provided for each major operation, with the operations involving lithographic masking called out with thicker lines, where possible. It must be noted that the illustration is for only a small microscopic area of a microprocessor that is one of hundreds of microprocessors that may populate a given 300-mm wafer at the end of the fabrication process. 

In Fig. 8.13(b), because Vgg is greater than Vdd + Vr, Vos is always smaller than Vgs — Vr, thus, the load always operates in the linear region. This results in a linear enhancement load NMOS inverter. The high value of Vgg also ensures that Vqs is always greater than Vj-, so that the load remains on and Vqh pulls up to VoD- The linear enhancement load configuration, however, requires a load transistor of larger area relative to the saturated enhancement load inverter, and requires additional chip area for the Vgg contact... 

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