Drain current, MISFET

Figure 14-8. Drain current-voltage characteristics of a typical MISFET for various gate biases.

However, such barriers are used and are created by special technology (enhanced types of MISFET). In this case, a voltage difference between the gate and source, Uqs, lower than or equal to the positive value of the so-called threshold voltage, U-r, cannot overcome the barrier and the transistor is shut (drain current, I, is zero). On the other hand, the depleted types of MISFET have negative values of Ux and even if Uqs < 0 is applied, the current Id can flow (for Uqs > Uj). In first-order MOS transistor theory, the dependence of Id on Ugs is described by... 

For MISFETs with the other type of channel, i.e. p-MISFETs, analogous rules hold. The major carriers in the n-substrate are then electrons and in the inverse conductivity layer the minor carriers are positive holes in crystallographic structure (slower than electrons). The drain current (Id < 0) rises with more negative applied voltage Ugs. 

Fig. 6. Dependence of drain current, on gate-source voltage, Uqs, for depletion type of n-MISFET at different temperatures. Uj, threshold voltage.

Fig. 21.52 MISFET characteristic (source/drain current vs. source/drain voltage for various gate voltages) of the device obtained after PPV implantation with iodine ions E = 30 keV and D = 4 x 10 ions/cm-).

Because there is no depletion layer between the substrate and the conducting channel, the equations of the current-voltage curves are in fact simpler in the TFT than in the MISFET, provided the mobility can still be assumed constant (which is not actually the case in most devices, as will be seen below). Under such circumstances, the charge induced in the channel is given, in the case of an /l-channel, by Eq. (14.23). In the accumulation regime, the surface potential Vs(x) is the sum of two contributions (i) the ohmic drop in the accumulation layer, and (ii) a term V(x) that accounts for the drain bias. The first term can be estimated from Eqs. (14.15), (14.16) and (14.19). In the accumulation regime, and provided Vx>kT/q, the exponential term prevails in Eq. (14.16), so that Eq. (14.15) reduces to... 

Figure 41. MISFET structure with Au source and drain contacts. Shown here is Ids versus Vds for various negative values of V gs, showing channel current enhancement and saturation.

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