Methods of Reducing Interconnect Delay

Electromigration Resistance (at 0.S ym) Poor Poor Fair- Poor Very Good Good Very Go(  

Corrosion Resistance Poor Good Good Excel Poor Good 

Adhesion to SiOj Poor Good Good Poor Poor Poor 

CVD Processing None None None Avail. Avail. 

---

Advanced metallization schemes are required to obtain the performance benefits of scaling device dimensions into the sub-0.5 pm regime. This section discusses the origin of the interconnect delay and impact on IC electrical performance. Methods of reducing interconnect delay will be discussed, including MLM and the use of new metal and ILD materials. As additional metal layers are added, surface planarization requirements increase. This section discusses planarity requirements while subsequent sections discuss planarization schemes, including CMP. 

---