Memory address space mapping

After the image has been successfully captured, the contents of the buffer memory may be mapped onto the address space of the Unibus of a PDP11/04 minicomputer for quantitive analysis, via a group of programs (SIM-1) (7). Approaches to analysis available to us include least squares fitting (5), eigen analysis (3). and... 

Table 3 shows how the various parts of the transform contribute to the total number of re-map operations. The total number of re-map operations roughly triples for each doubling of the data size. If a re-map operation takes 2 msec to re-define the CPU s address space, then approximately 3 sec or 5% of the total time of a 16K-16K transform is used for this purpose. If parts of the virtual array reside on disk, however, disk I/O will substantially increase the time required for an individual re-map operation. Clearly, the bit reversal routine becomes the least efficient of all the routines if memory re-mapping is slow. The execution times for the parts of the transform are shown in Table 4. Computationally, the least efficient routine is the final passes, because the algorithm used in the final passes is slower (by a factor of more than two) than the algorithm used for the internal transforms.

Systems that support virtual memory (that is, have the requisite hardware support) normally support a single virtual address space which all active processes share. Some systems, however, support multiple virtual address spaces one for each active process. This technique is termed virtual machine and requires additional complexity in the mapping functions and associated hardware. 

The MMU controls whether the VIC chip or 80-column chip controls screen display, and even senses the position of the 40/80 DISPLAY switch (though the software must interpret this switch). The MMU controls access to RAM or ROM, allowing either to be visible in the memory map. A programmer can set up a series of preset memory configurations and quickly select them by writing to the MMU. The address of the VIC chip can be relocated an5rwhere within the virtual 256K memory space. 

To receive data from the Ethernet line, the host CPU sets aside an adequate amount of buffer space and invokes the co-processor by writing to a memory mapped address. The co-processor responds by requesting bus control, and then reading the command instruction from memory. Upon enabling the coprocessor in receive mode, the asynchronously arriving data frames are stored into a free memory area. Once an entire error-free frame is received, the coprocessor fetches the adress of the next free receive buffer and interrupts the CPU. Transmission of data is performed in a similar manner. 

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