Mellons System Architects Workbench

extended to support processes and message-passing interprocess communication, and user-definable operations. 

using CAD Language Systems, Inc. s parser. Transformations / APARTY / CSTEP / EMUCS Synthesis Path Internal Behavioral Representation 

Uses the Yalue Trace (VT), a dataflow / controlflow graph. Transformations 

The CSTEP control step scheduler uses list scheduling on a block-by-block basis, with timing constraint evaluation as the priority function. Operations are scheduled into control steps one basic block at a time, with the blocks scheduled in executi m order using a depth-first traversal of the control flow graph. For each basic block, data ready operator are considered for placement into the current control step, using a priority function that reflects whether or not that placement will violate timing constraints. Resource limits may be applied to limit the number of operators of a particular type in any one control step. 

In a post-processing phase, Busser then adds buses to the design, replacing multiplexors as necessary. A compatibility graph is 

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This book presents the results of several coordinated research projects, collectively referred to as the System Architect s Workbench the Workbench). These research projects were Ph.D. Theses completed under the direction of Professor Donald Thomas and granted by the Electrical and Computer Engineering Department of Carnegie Mellon University. The research described here fits into the first two design steps of Figure 1-1 and can be grouped into three major categories ... 

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