Low Dielectric Constant ILD

As mentioned in Chapter 1, the present state of CMP is the result of the semiconductor industry s needs to fabricate multilevel interconnections for increasingly complex, dense, and miniaturized devices and circuits. This need is related to improving the performance while adding more devices, functions, etc. to a circuit and chip. This chapter, therefore, discusses the impact of advanced metallization schemes on the performance and cost issues of the ICs. Our discussions start with the impact of reducing feature sizes on performance and the need of various schemes to counter the adverse effect of device shrinkage on the performance of interconnections. An impact of continued device shrinkage on circuit delay is discussed. Then the need of low resistivity metal, low dielectric constant ILD, and planarized surfaces is established leading to the discussion of CMP. Finally various planarization techniques are compared to show why CMP is the process that will satisfy the planarity requirements of the future. 

One example of a successful polymer CMP program is for the fabrication of ILD layers for multichip modules (MCM) at MCC. Figure 8.7 shows schematically a cross section view of an MCM interconnection system. Low dielectric constant ILDs are required in MCMs because the long interconnect lengths lead to long delays. In the MCC process, the polyimide is deposited by... 

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