Interconnect 5,83 netlist

In this chapter, we assume that the synthesis process produces a synthesized netlist in Verilog HDL as shown in Figure 5-1. A Verilog HDL netlist is a collection of module instances interconnected by nets. 

To do this, first from the circuit schematic, a netlist is extracted. This Hst contains exact information about which node of a given element is connected to which nodes of other elements. This netlist is then submitted to the place and route program. This program places all of the elements or cells in the circuit on the gate array, in a fashion similar to what was done in Fig. 8.79, and attempts to connect them as specified in the netlist. The program may iterate the placement of cells and interconnection or routing until all cells Hsted in the netlist are placed on the gate array and interconnected as specified. 

Net and Netlist A net stands for a conductor that interconnects two or more component terminals. Netlist is a description of the connectivity of an electronic circuit. In its simplest form, a Netlist consists of a list of the terminals of the electronic components in a circuit and a list of intercormecting electrical conductors. As a programming file of the FPGA contains the Netlist information. 

In the schematic stage, components and their interconnection pattern (netlist) are defined, simulated, and verified for functionahty using schematic capture tools such as Mentor s Design Architect and Cadence s Concept. (The schematic interconnection list is usually called schematic netlist. It is an electrical network-based grouping of connection points of... 

The 3D geometries of the electronic components are stored in a device library. Pin mapping, land patterns, and electronic (e.g., functionality), mechanical (rigidity, elasticity, etc.), and thermal properties (heat conductivity, etc.) are all included in the dataset. The components can be read from the library on the basis of the netlist from the ECAD tool Eagle. The components can be positioned on the three-dimensional interconnect device freely on analytically describable surfaces, and keepout areas (e.g., dummies for holes to be drilled) can be defined in advance. 

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