Function signal assignment

For a combinational process, it has been shown in [12] how to eliminate the internal variables, and compute the transition function of all signals assigned in the process, as a set of concurrent signal assignments. In this section we will only illustrate a conditional form on a simple example in the two languages ... 

Local formulas correspond to each type of statement in the VHDL subset. In general, the formalization of a statement consists of two parts flow and function. The flow component captures the program flow implicit in the statement. In traditional procedural languages, flow proceeds from one statement to the next, except for loops and selection statements. In VHDL, the situation is complicated somewhat by the presence of a time dimension for certain statements (e.g. WAIT). The second component of a statement formalization is the functional component, and captures the semantics of the variable values affected by the statement. The functional component is complicated by the presence of statements that affect variable values at a different time (e.g. signal assignment). 

Fig. 7. Signal assignment in high field region of 300-MHz proton NMR spectrum of neurotoxin II in D O solution at pH 7.3 and 32°C. A - Normal spectrum. B - resolution enhanced spectrum by means of a triangular function(41).

DATAFLOW4 is an example of another concurrent statement, a selected signal assignment. This performs a similar function to die conditional sig-... 

Let us look at some of the traps it is easy to fall into when making sequential signal assignments. The following examples are simple but bad versions of the D-type flip flop. The function of each should be clear without showing the associated entity ... 

A function is very similar to a Process statement in its operation except that it cannot contain signal assignment or Wait statements. This means that a function caimot be used to create sequential logic. As the RIPPLE functions illustrate, variables that are local to the function can be declared in the declarative part and its execution is sequential. All objects declared locally are discarded when the final result is returned. The s)mtax of a function and other important details are given in Box 6.4. 

Any sequential statements can be used in a function except a Signal assignment and a Wait This means that a function cannot infer a sequential block of logic. 

Look at the example architectures that call this package s functions in Figures 6.5-6.7. The architecture RIPPLE I calls the function RIPPLE in a signal assignment expression. How does the synthesizer know which version of RIPPLE is being caUed In this case die number of parameters in the parameter list reveals which version is required. As there are only two, it is the first version. In this example, therefore, the first RIPPLE function has overloaded die second owing to the parameter count. This function returns an overflow bit attached to the result. This is extracted and the outputs, ANSWER and OVERFLOW are assigned. 

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