Flip flop signal value assignment

The architecture BAD I assigns the flip flops output values, Q and QBAR, inside the process. The rules for inferring flip flops state that any signal assigned inside a synchronous section becomes the output of a flip flop. This description therefore infers two flip flops as shown in Figure 5.32. 

The sequential statements inside die If must assign a value to a signal or to a previously undefined variable for the synthesizer to infer a flip flop and hence create a registered output. Otherwise, purely combinational logic will be generated. 

The architecture BADJK, uses two signals to store the present states of the flip flops inverted and non-inverted outputs, SBAR and S. The Case statement inside the S3mchronous section is used to determine the new state of S and assign its value. The value of S is then passed on to SBAR at the end of the Case statement. Unfortunately, the new state is not registered on the flip flop inferred for S until the end of the process so the SBAR will be assigned the old state of S. If this is not bad enough, because SBAR is assigned inside the synchronous section, it also infers another flip flop ... 

---