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Etching of polyimide

Usually, dry etching of polyimide is performed by RIE with O2, CF, or their mixtures as an etchant gas, utilizing positive photoresist (2), metals such as aluminum (3), spin-on-glass (4), or SiN (5) as an etching mask. However, in the former case, it is difficult to define a fine via-hole as small as 2 pm or less because the resist thickness must be two or more times that of the polyimide as a result of the equal etching rates between photoresist and polyimide. In the latter case, though the fine pattern can be obtained the additional pattern transformation from the photoresist to the masking layer is necessary. [Pg.547]

For asymmetric etching of PC or PET, one side of the membrane is put in contact with an alkaline etching solution, usually 9 M NaOH or KOH, and the other side is in contact with the stopping medium, typically a weak acid solution such as 1 M HCOOH in 1 M KCl (30). For asymmetric etching of polyimide (Kapton), the etching solution is NaClO... [Pg.685]

Davis et al. reported the successful etching of PTFE using single-photon energies in the quartz UV (308 nm and a pulse duration of 25 ns) by sensitizing the fluoropolymer with polyimide. 72 The number of pulses varied depending on fluence and material composition in order to achieve ablated features whose depths were reproducible as measured by a stylus-type profilometer. The pulse repetition rate was on the order of about 200 Hz. In that study, dopant levels... [Pg.21]

Schematic of the Si-nMEA fabrication process (a) sputter Au layer on double-side polished wafer (b) pattern Au layer with liftoff process (c) spincoat and cure a polyimide layer (d) perform the double-sided photolithography to pattern etch pits (e) etch Si in ICP-DRIE to form Au/Si electrode (f) dice the wafer into a single die (g) RIE etch the polyimide layer with a shadow mask to expose current collecting region (h) electroplate Pt black on Au layer (i) sandwich both electrodes with Nafion 112 in a hot-press bonder. (Reprinted from J. Yeom et al. Sensors Actuators B107 (2005) 882-891. With permission from Elsevier.)... Schematic of the Si-nMEA fabrication process (a) sputter Au layer on double-side polished wafer (b) pattern Au layer with liftoff process (c) spincoat and cure a polyimide layer (d) perform the double-sided photolithography to pattern etch pits (e) etch Si in ICP-DRIE to form Au/Si electrode (f) dice the wafer into a single die (g) RIE etch the polyimide layer with a shadow mask to expose current collecting region (h) electroplate Pt black on Au layer (i) sandwich both electrodes with Nafion 112 in a hot-press bonder. (Reprinted from J. Yeom et al. Sensors Actuators B107 (2005) 882-891. With permission from Elsevier.)...
An aluminum etching mask is deposited (Fig. 14 e) and patterned corresponding to the shapes of the devices. RIE is used to etch the polyimide down to the support wafer and to separate all devices in one etching step. After removing the aluminum and the resist, the single devices are separated from the support wafer. The resulting components have a total thickness of 10 pm (Fig. 14 f). [Pg.148]

Compared with conventional photolithography, laser drilling is a dry process and keeps the surface of polyimide gate dielectric layer away from water, etching solution, or other solvent, which often degrade the polyimide surface. We have confirmed that the electronic performance of transistors with laser via holes is identical with that without laser via holes. [Pg.398]

Kapton polyimide has been widely used in the electronic industry because of its low dielectric constant, good mechanical properties and high thermal stability. Many applications require good adhesion between Kapton polyimide film and metal. Various processes to improve adhesion of metal to Kapton polyimide have been reported in the literature. DeAngelo et al., (D describe a process to form metal oxides on the surface of polyimide to improve adhesion. Other efforts to improve adhesion of a metal layer involve roughening of the surface of polyimide substrate by methods such as cathodic sputtering (2), chemical attack (2., 1), and reactive ion etching (1,4). [Pg.235]

With the increase of the degree of integration of microcircuits, the multilevel interconnect technology becomes inevitable for future VLSI manufacture. Polyimide exhibits superior planarity over stepped structures and is expected to be one of the most promising materials for the dielectric insulation of VLSI s. However, since the smallest via holes so far achieved by wet etching is 3 pm (1), the formation of fine via holes by a dry etch process is needed for the application of polyimide to VLSI having fine metal wiring. [Pg.547]

Fig. 14 SEM photographs of polyimide patterns with CVD tetravinylsilane film as an etch barrier (a) a stencil mask used, (b) (b),(c) polyimide patterns of (PMDA-ODA) vapor deposited. Fig. 14 SEM photographs of polyimide patterns with CVD tetravinylsilane film as an etch barrier (a) a stencil mask used, (b) (b),(c) polyimide patterns of (PMDA-ODA) vapor deposited.
Fig. 77 Nanosecond expansion/etching behavior of polyimide after 248- and 351-nm irradiation. REPRINTED WITH PERMISSION OF [Ref. 223], COPYRIGHT (2002) Elsevier Science... Fig. 77 Nanosecond expansion/etching behavior of polyimide after 248- and 351-nm irradiation. REPRINTED WITH PERMISSION OF [Ref. 223], COPYRIGHT (2002) Elsevier Science...
An example of chemical etching is seen for polyimide/silica composite prepared by sol-gel method [Morikawa et al., 1992]. After chemical etching of the polyimide matrix with hydrazine. [Pg.555]

Figure 2. Etch depth profile of PMMA film obtained with 248 nm ( ) excimer laser irradiation and that of polyimide film obtained with 248 nm(0) and 351 nm(0) excimer laser irradiation. Negative etch depth means permanent swelling. An error bar is included. Figure 2. Etch depth profile of PMMA film obtained with 248 nm ( ) excimer laser irradiation and that of polyimide film obtained with 248 nm(0) and 351 nm(0) excimer laser irradiation. Negative etch depth means permanent swelling. An error bar is included.
A possible procedure for synthetic jet fabrication has been shown in Fig. 3. The first step in the fabrication process is the wet etching of the silicon wafer using KOH to form a cavity. The cavity is filled with electroplated nickel in the second step. A polyimide membrane is deposited over the silicon wafer using spin coating in the third step. The back side of the silicon substrate is etched using KOH to obtain the orifice hole. The orifice hole extends till the filled nickel inside the cavity and the nickel material are also etched away. The piezo-ceramic material is deposited on top of the membrane for actuation. In case of electrostatic-based actuation, aluminum electrode is deposited on the membrane. [Pg.3377]


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See also in sourсe #XX -- [ Pg.94 ]




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