Design process, VHDL synthesis

Honeywell s V-Synth (VHDL-Synthesis) System decomposes VHDL descriptions into simple statements, optimizes those statements with compiler-like transformations, schedules the operations into states, and then passes the resulte to the MIMOLA Synthesis System to complete the design process. See also Univ, of Kiel s MIMOLA System. 

Figuie 2.2 Design process with VHDL logic synthesis software. 

To start architectural synthesis, an initial data flow analysis is required. It is also this process which resolves the very different nature of current designer interface languages (Vhdl, HardwareC, Silage,. ..). By standardization on the result of this analysis, the input alternatives become available for all the synthesis projects. 

It is possible to write VHDL code that the synthesizer cannot cope with. For example, relatively few synthesis tools can support division operations. Furthermore, some VHDL design styles are impossible for die synthesizer to analyse successfully. As time progresses, research into these issues means that the capabilities of the software ate continuously improving, but nonetheless substantia] limitations exist. It is a major aim of this book to communicate techniques that enable the writing of VHDL code that can readily be processed by logic synthesis software. 

This chapter has been a case study of the processing element architecture of the toroidal neural processor. The simple aim has been to present a complete design that incorporates a wide range of the VHDL constructs and synthesis ideas and issues that were introduced in the earlier chapters. It is hoped that the reader will perform some of the suggested exercises linked to this case study and discussed in the text. 

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