Challenges to Silicon IC Manufacturing

Also note that this and subsequent sections use logie ICs as a basis for discussion. However, memory ICs use CMP broadly for many of the same applications as logic ICs do, as well as some applieations unique to memory. In general, the challenges faced by CMP in logic IC production apply to memory IC production. 

Throughout the past 40 years, the industry has maintained Moore s law by shrinking the dimensions of the ICs components. At smaller dimensions, transistors switch faster and the density of transistors increases. Hence, shrinking allows the circuit to run faster and the circuit designer to add more functionality. A basic recipe for maintaining Moore s law is to release a new technology every 2 years that scales circuit dimensions by 30% (linear) and increases transistor 

FIGURE 20.4 (a) Gordon Moore s prediction in 1965 that the level of integration 

The need for the CMP processes described in Table 20.1 arose as a direct result of shrinking circuit dimensions. In each case, a challenge arose and a CMP process was used to meet that challenge. The question for the CMP technologist is what are the future challenges to the IC industry and will CMP be used to meet those challenges The remainder of Section 20.2 will 

FIGURE 20.5 Exponential increase in the performance of Intel Corp. microprocessors as measured in MIPS (million instructions per second) (from Ref. 3). 

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