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Ceramic dual in-line package

With the conventional technology, ICs are mounted individually in plastic or ceramic single-chip packages (SCPs), such as dual-in-line packages (DIPs) or chip carriers, and the SCPs are interconnected on printed wiring boards (PWBs). The number of pins on SCPs has increased significantly, and line widths on PWBs, like IC feature sizes, have followed a historical downward trend (2). However, the basic SCP-on-PWB approach has remained predominant. [Pg.450]

Adhesives are also tailored to meet specific requirements of the packaging or assembly technology used (Table 5.9). Thus, the requirements for single-chip packaging in hermetically sealed ceramic packages such as CERDIPs will be somewhat different from those of plastic dual-in-line packages (PDIPs) and plastic-encapsulated microcircuits (PEMs). [Pg.242]

See other pages where Ceramic dual in-line package is mentioned: [Pg.713]    [Pg.13]    [Pg.380]    [Pg.13]    [Pg.434]    [Pg.856]    [Pg.14]    [Pg.436]    [Pg.683]    [Pg.713]    [Pg.13]    [Pg.380]    [Pg.13]    [Pg.434]    [Pg.856]    [Pg.14]    [Pg.436]    [Pg.683]    [Pg.477]    [Pg.19]    [Pg.16]    [Pg.13]    [Pg.211]    [Pg.1345]    [Pg.14]    [Pg.38]    [Pg.351]    [Pg.352]    [Pg.412]    [Pg.277]    [Pg.700]    [Pg.321]   
See also in sourсe #XX -- [ Pg.683 ]



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Ceramic package

Dual-in-line

Dual-in-line package

In ceramics

In line

In packaging

In-Ceram

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