Casex statement

In a casex statement, the values x and z ( for a z is ok too) in a case item expression are considered as don t-care values. These values, for synthesis purposes, cannot appear as part of the case expression. Here is an example of a casex statement used to model a priority encoder. 

Figure 2-32 A priority encoder using casex statement.

The semantics of this casex statement can best be expressed by its equivalent if statement. 

The rules for inferring latches apply to casex and casez statements equally as well. 

Verilog HDL semantics of a case statement specifies a priority order in which a case branch is selected. The case expression is checked with the first case item, if it is not the same, the next case item is checked, if not the same, the next case item is checked, and so on. A priority order of case item checking is implied by the case statement. Additionally, in Verilog HDL, it is possible for two or more case item values to be the same or there may be overlapping case item values such as in casex and casez statements however, because of the priority order, only the first one in the listed sequence of case items is selected. 

When value x is used in a case item of a case statement (not casex, casez), the branch corresponding to that case item is considered never to execute for synthesis purposes. 

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