Buried systems well casings

Without preamplification surface state trapping noise will still be a problem for 3-5 pm systems for TDI clocking frequencies over 10 kHz however since the CCD can be fabricated in silicon a buried channel device could be used to circumvent this noise problem. In any case a tapered register is usually used for TDI as shown in Fig. 6.8 to provide a constant fat zero from the background. With this hybrid approach the CCD well width is not directly related to the photoactive area so that saturation problems can be relieved by using a wide register near the end, but this increases the separation requirement between TDI channels, complicating focal plane layout since no more than a 2 1 interlace is desirable. 

This is the common form of buried capacitance. Most bare board test systems are not well suited to measuring capacitance values, particularly small ones. In some cases, no measurement is specified and it is only important that the test system tolerate the presence of the capacitance. When measurements are specified, it is usually true that few test points are involved. It may be expedient to use benchtop equipment. 

---