Architectural Partitioning

Architectural partitioning divides the behavior of an architecture onto separate physical units. Several criteria are important in deciding how the behavior should be divided. The most important architectural partitioning considerations are described below. 

Two types of partitioning that address these performance issues are discussed below. 

Since complete instructions (or groups of complete instructions) are implemented on single partitions, the partitions have the potential for concurrency. Thus, each partition could be implemented as a separate process if data dependencies are satisfied. An additional benefit of this type of partitioning is that the data paths on each partition may be simplified because each partition implements only a subset of the total instruction set. A simpler data path may allow for a faster clock rate, and thus better performance for the design. 

Extended Processing Units (EPUs) to execute floating point instructions. 

Several instruction set partitions for the IBM System/370 are described in [Agnew82]. None of the methods took advantage of concurrency available at the instruction level. However, they represent a range of performance due to the way that the instruction set is partitioned in each case. The partitions are discussed in greater detail in Section 4.6.2. 

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E. Lagnese and D. Thomas, Architectural Partitioning for System Level Design, Proc. 26th Design Automation Conference, pp. 62-67, ACM/IEEE, June 1989. 

System overview, design representations, transformations, architectural partitioning, scheduling, data path synthesis, microprocessor synthesis, a fifth-order digital elliptic wave filter example, a Kalman filter example, the BTL310, the MCS6502, and the MC68000. 

E. Dirkes Lagnese and D.E. Thomas, "Architectural Partitioning for System Level Design , Proc. of the 26th DAC, pages 62rSl, June 1989. 

Architectural partitioning, guiding CSTEP, EMUCS and Busser, and a fifth-order digital elliptic wave filter example. 

Elizabeth Dirkes Lagnese, Architectural Partitioning for System Level Design of Integrated Circuits, PhD Thesis, Dept of Electrical and Computer Engineering, Carnegie Mellon University, March 1989. 

Overview of the system, transformations, control step scheduling, architectural partitioning, synthesis using... 

The Architectural Partitioning tool (APARTY) proposes the major structural features of the design from the transformed behavior. The tool suggests how certain behavioral operators should be grouped and implemented by common hardware. 

The Control Step Scheduler (CSTEP) schedules the behavioral operations into control steps, determining the parallelism of the design. It considers the structural partitions suggested by the Architectural Partitioning tool as well as timing and resource constraints specified by the designer. 

To choose architectural partitions, APARTY uses a unique multistage clustering technique. Multi-stage clustering, which is described in Section 4.3, is based on an established clustering algorithm that has... 

Multi-stage clustering allows operators to be considered as groups. This is particularly appropriate for architectural partitioning where large groups of operators are considered. 

Comparison. This cluster stage is very similar to the clustering done by McFarland and Rajan, however multi-stage clustering allows groups of operators to be considered, making this more appropriate for the architectural partitioning application. 

Architectural Partitioning none none none none 2 data partitions... 

Microprocessor Implementation of Mainframe Processors by Means of Architecture Partitioning. 

Architectural Partitioning for System Level Design of Integrated Circuits. 

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