A diagram of computer system

With the stacked DRAM, the off-chip delay can be almost completely removed since no off-chip wires and I/O pads are necessary. Of course, it still too early to use an exact latency value for the stacked DRAM at the present due to the inviolability of technology parameters. Assuming a 400-cycle off-chip memory latency, we set the upper bound latency (pessimistic estimation) of stacked DRAM is 300 cycles, while a lower bound latency (optimistic estimation) is 200 cycles. 

Today a typical off-the-shelf 1 G-bit DRAM in a 0.13 pm process has a die size of 204 mm2 81, Such a DRAM die can hold 192 MB if we assume it would have the same die size as the microprocessor. Certainly this capacity is too restricted with today s standard. To have a larger capacity, we could consider the following three options  

Stacking more layers of DRAMs on the top For instance, when 3 layers of DRAM dies are stacked on the top of the microprocessor die, 576 MB is available, which is applicable for most applications. A 5-layer DRAM could suffice high-end applications. The major concern of such a configuration is heat dissipation. Fortunately, DRAM usually has relatively low power consumption. If there s still excessive heat build-up, hardware based heat dissipation techniques like heat pipes (e.g., dummy inter-chip interconnects) have to be installed. 

Stacking a larger DRAM die Having a larger die provides higher memory capacity, but certainly requires a bigger footprint than that of the bottom layer microprocessor. The over-sized DRAM dies may pose difficulty to the package. 

Installing extra off-chip main memory The stacked DRAM and off-chip DRAM have different access delays and thus this approach implies a Non-Uniform Memory Architecture (NIJMA)1231. The operating system has to take charge of the resultant memory management issues. 

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