With Synchronous Preset and Clear

What if we want to model a flip-flop with synchronous preset and clear In such a case, simply describe the synchronous preset and clear logic within a clocked always statement (an always statement with a clock event). Here is an example. 

There are two approaches to synthesize this model. One approach is to direct the PresetData input into the synchronous preset input of the synthesized flip-flops alternatively, the PresetData could be directed directly into the data input of the flip-flops. The synthesized netlist shown here shows the latter option a synthesis system may optionally synthesize to the alternate approach. 

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From this example, it appears that all the inputs to NextState, the value 12, the value 5, and the variable CurrentState, should be multiplexed using appropriate select lines into the D-input of the inferred flip-flops for Next-State. This is exactly what occurs as shown in the synthesized netlist in Figure 2-55. So then, how can we infer flip-flops with synchronous preset and clear A synthesis system may provide a solution for this by providing a special option for directing the synthesis system to generate a synchronous preset clear flip-flop. 

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