Wire length reductions of mixed placement

5-D placement tools could serve as the starting point to develop a full-fledged placement tools set for future 2.5-D/3-D ICs. Specifically, future 

5- D placement tools have to be able to optimize multiple cost objectives in addition to the traditional wire length and critical path delay. 

5- D placement can be followed by a routability driven migration process so that the demand can be lowered by moving the least number of place-able objects. 

Hot-spot avoidance To guarantee the correct functionality of an IC, the heat generated by devices and wires must be effectively and efficiently removed. The 

5- D placement tool has to generate solutions with a relatively even thermal map and low peak temperature. There has been a large body of work (e.g., [16,17]) proposed to solve the problem. For analytical based placers, the requirement for an even thermal can be formulated as a set of equations as constraints. On the other hand, under the context of partitioned based placement, a high power cell can be bloated to a certain extent so that it can be allocated with a larger white space and thus lower power density. 

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Figure 6.11 Wire length reductions of mixed placement...

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