Wafer-level 3D using adhesive bonding

Another 3D demonstration that used adhesive bonding included In-Au microbumps for interwafer interconnection and was reported by Lee et al. in 2000 [45]. A large shared cache memory was stacked above a processor to enable memory-intensive applications such as multiple processor computing, using 1.5-pm gate-length technology and doped polysilicon. 

FIGURE 15.7 A schematic of the wafer-level dielectric adhesive bonding via-last approach to 3D demonstrated by Lu et al. (from Ref. 46-50). 

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