Synthesis multiple objective function

The object-oriented emphasis on the separation of the interface of an object from its operation is mirrored dosely in VHDL. In this case the entity provides the interface specification to the circuit and die architecture (implementation) of the drcuit provides the functionality. Moreover, the same entity can have multiple architectural representations, thus providing a range of descriptions for die same component. T3rpically, this is of use in top-down design, in which a behavioural description can be modelled first and die design incrementally refined towards a more detailed structural description. Where logic synthesis tools are involved it is possible to have multiple descriptions of the same circuit and it is easy to experiment with die s)mthesis tool to find out which instantiation of die circuit iimction is the most suitable. 

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