Solderability Testing Plated through hole

PCB Surface Finishes and Solderability Testing for Plated Through Holes... 

J-STD-003, Solderability Tests for Printed Boards. J-STD- 003, Solderability Tests for Printed Boards, was released in April 1992 to complement the requirements of J-STD-001. This standard prescribes the recommended test methods, defect definitions, and Ulnstrations for assessing the solderability of printed board surface conductors, attachment lands, and plated-through holes. 

Laminates based on Rhone Poulenc s Keramid 601 polyimide resin are fabricated in a conventional laminating press, and processed in a manner similar to that used for epoxies but with an extended cure cycle or post-cure. The room-temperature mechanical and electrical properties are similar to epoxy laminates, as shown in Table 9.4. At elevated temperatures, the polyimides exhibit exceptional stability. In particular, the thermal coefficient of expansion in the Z axis does not change significantly up to approximately 240°C, as shown in Fig. 9.11. Exhaustive tests have shown that polyimide-based multilayer boards can withstand repetitive thermal cycling at elevated temperatures (>150°C) without cracking of plated through holes. Similar excellent results were also obtained in solder shock tests (10 s at 288°C in molten solder). The thermal stability of these materials is retained at temperatures of approximately 200°C for continuous exposure in air, which has qualified them for military applications. 

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