Random sequence generator

A random sequence generator starts from a seed and produces a new Sequence of output bits whenever it receives a clock pulse. It is only a pseudorandom sequence however, as the same seed will always produce the same following sequence. 

This section demonstrates die use of only one new statement - the procedure in the design of two forms of the generator. It also shows new important examples of statements and important approaches demonstrated or discussed in previous sections. These include  

The Procedure statement is also special in that it may be used in both concurrent and sequential sections of code. The two examples below will demonstrate this. 

Internally, the random sequence generator operates by shifting all the bits one position to the right and creating the new left bit through an Xor function on two of the other bits. This will be demonstrated clearly in the VHDL. 

This calls for the use of three-state buffers, encountered in the last section. 

---

Randomization -Sequence generation 8 Method used to aenerate the random allocation seauence, includina detaiis of anv restriction (e.a.. blocking, stratification). ... 

Figure 7.16 The inputs and outputs from the top-level blocks in the two variants of the random sequence generator...

The procedure that describes the operation of the random sequence generator is stored in a package called CONTROL.LOGIC in the working library. The details of the prcKedure itself are discussed below. 

RSG I-BEHAVIOUR is the entity-architecture pair for the simple random sequence generator circuit. It is shown in Figure 7.17. 

Figure 7.17 Simple random sequence generator with reset.

Figure 7.18 CONTROL LOGIC package containing random sequence generator.

This behavioural description requires the buffers contained within the BUFFERS block to enable and disable the input and output ports connecting die random sequence generator to die external bus. The code demonstrates another way of declaring and defining a procedure - bodi the procedure declaration and body are contained within the entity declarative part. 

Figure 7.19 Random sequence generator with external seed.

The random sequence generator has particularly demonstrated die use of the procedure as bodi a concurrent and sequential statement. The function itself is quite simple. A loadable seed value has enabled the use of three-state buffers plus the effect of a bidirectional signal to be demonstrated. The optimization statistics clearly hig ighted the effect that these buffers have on the performance of the circuit. 

The sequence follower example architectures demonstrated a good approach to the design of state logic using a nested case structure. The random sequence generator used a module-based design to illustrate the benefit of procedures (or even functions) that are designed to be portable. 

The component REGISTERS contains all the register and ports that were shown in Figure 8.6. The ALU block has been broken up into its two constituent parts, the adder and die random sequence generator. Also note that the RAM shown in Figure 8.6 has not been designed. 

---