Programming language / VHDL

As with any programming language, VHDL requires a meffiod for storing data or transferring it to another section of the code. An object is a named entity or element that contains a value of a given type. There are four classes of object in VHDL - constants, signals, variables and files. The final class will be ignored by a synthesizer as it is used to access or store information in the host system environment. The others are discussed below. 

VHSIC Hardware Description Language (VHDL) is a widely used hardware description language which has become a standard in many domsuns. A common traditional use of VHDL has been to construct VHDL descriptions modeling the hardware design and then simulate the VHDL program to show that it meets a set of informal specification criteria from which test vectors have been generated. However, this approach is often insufficient in critical applications where it is desirable to prove that the VHDL description meets a set of formally specified correctness criteria, and a formal semantics of VHDL is thus needed. 

Breuer, P., Delgado Kloos, C., Marm Lopez, A., Martinez Madrid, N. Sanchez Fernandez, L. (1997), A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL , ACM Tmnsactions on Programming Languages and Systems 19(4), 1-30. 

Design entry in a high-level synthesis system is an algorithmic description written in a common programming language (like PASCAL or FORTRAN), or by a special purpose hardware description language (HIX), such as ISPS, DSL or VHDL. 

Farrow, R and Stanculescu, A. G (1989) A VHDL Conquler Based on Attribute Grammar Methoddogy. ACM SIGPLAN Conference on Programming Language Design and Implementation, pp 120-130. 

Figures shows a VHDL description for the dequeue processor of Figure 1. he initial steps of the translation of the VHDL processes into a BFSM are the same as those used in standard programming language comfulation. The first step is...

VHDL allows the use of explicit time delays. It is possible to say that a statement is executed after a certain time delay. This is in sharp contrast to programming languages in which there is a concept of sequence but not delay. Specific time delay procedures are often supplied as part of a programming language support suite, but they are not part of the language themselves. VHDL constructs explicitly model the time delay inherent in all electronic circuits. At this point it is perhaps pertinent to... 

All four methods will create an object that can be referenced by name but only the first method is an explicit declaration. The other three will create the object implicitly for use only within a restricted section of code, such as a subprogram or loop. The rules governing where a declared object can and cannot be used are similar to those in other programming languages but will be clarified where necessary. The naming of VHDL objects is discussed in Chapter 4. 

Like other programming languages, the two t3rpes of subprogram available in VHDL are functions and procedures. The built-in arithmetic operators all call functions and so these will be used in this case. Procedures are more flexible than functions and are discussed further in Qiap-ter 7. 

Local formulas correspond to each type of statement in the VHDL subset. In general, the formalization of a statement consists of two parts flow and function. The flow component captures the program flow implicit in the statement. In traditional procedural languages, flow proceeds from one statement to the next, except for loops and selection statements. In VHDL, the situation is complicated somewhat by the presence of a time dimension for certain statements (e.g. WAIT). The second component of a statement formalization is the functional component, and captures the semantics of the variable values affected by the statement. The functional component is complicated by the presence of statements that affect variable values at a different time (e.g. signal assignment). 

---