Placement benchmarks

In our placement experiments, we assume a fixed-die, over-the-cell routing model. Thus, the layout area of a design is the footprint of all cells plus 10% free space. The 2-D layout is mapped to a 2.5-D layout consisting of two stacking chips with equal area. All layouts have a square shape. Thus, the dimension of two chips in 2.5-D system is that of the corresponding 2-D layout scaled by 0.707. For every benchmark circuit, we generate both monolithic (2-D) placement and 2.5-D placement. 

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Table 6.1 Placement benchmarks A. PicoJAVA and SPARC benchmark...

Dragon Placement benchmark, [online]. Available http //www.cs.ucla.edu/ xjyang/ Dragon/. 

The first test usually performed with a docking tool is the reproduction of complexes with known structures. The results achieved with docking algorithms are quite difficult to compare for several reasons. First, there is no unique benchmark set and every method is published with a small set of test results only. Second, different levels of a priori knowledge are used in the preparation of the input data and in the calculation. Examples for a priori knowledge are the definition of the active site, the placement of polar... 

In the benchmarks listed in Table 6.4, the largest area percentage of total chip area occupied by a single macro is below 14%, which is relatively small. Therefore, we believe we can still use the top-down partitioning technique in the placement if we carefully control the cut line during partitioning. Unlike the case of standard cell placement, where we can use the available tool for the monolithic problem, now we have to build both monolithic and 2.5-D placement tools. Again we developed this tool on the basis of UCLA s Capo placer. 

The classification and benchmarking of placement machines depend on different influence coefficients. In addition to accuracy and placement rate, placement rate per investment, placement rate per needed area, operation, maintenance, and flexibility have to be considered. In the future, flexible... 

Papa DA, Adya SN, Markov IL (2004) Constructive benchmarking for placement. GLSVLSI 2004, pp 113-118... 

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