Novel CMP for Next-Generation Devices

1 The Progress of Semiconductor Devices upon Current Demand 

FIGURE 6.2 Technical roadmap for DRAM and NAND flash memory. 

2 Complementary Metal-Oxide Semiconductor (CMOS) Memory 

Fulfilling multilayer and miniature structures of memory devices led to the introduction of new materials and sfrucfures. For the structure, the design rule decreases less than 70 nm and the short channel effect (SCE) phenomenon appears to have a bad influence on fhe device drive if exisf-ing planar transistor (TR) is applied. To solve this problem, studies are in progress to apply recessed charmel array TR and three-dimensional structured FinFET in DRAM and floating gate, twin SONOS, and FinFET SONOS in flash memory (Eigure 6.3). 

New materials are applied to maximize the capacity of device. To increase the capacitance of cap used in DRAM, sfudies about high-k dielectric material are in process. Elash memory uses a gate material with polysilicon by reason of high speed and stable storage. To reduce semiconductor device RC delay, Cu metal lines and low-k are being introduced. This section represents the concept of CMP processing being introduced to DRAM and NAND flash devices. 

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