Normalized clock rate vs. peak memory bandwidth of NVidia

It turns out that the 2.5-D regime is an ideal solution for a tiled multiprocessing architecture. The logic tile can be mapped to a high-performance CMOS chip and DRAM tiles can be allocated to a dedicated DRAM chip. The interface between logic and DRAM can be through inter-chip interconnects. With memory chips 

5-D integration scheme provides a natural solution for future wireless chipsets where hybrid technology parts have to be integrated. We envisage that the next milestone of 2.5-D integration would be its deployment in the wireless terminals. 

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Figure 7.5 Normalized clock rate vs. peak memory bandwidth of NVidia...

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