NMOS transistor fabrication

Example NMOS Fabrication. The individual steps listed in List I can be sequenced to give a simple process for the fabrication of an NMOS transistor (Figures 12 and 15) Although the example is a MOS transistor, the techniques also apply to the fabrication of bipolar transistors, diodes, capacitors, resistors, and ICs. 

Figure 15. Simplified process sequence for the fabrication of an NMOS transistor (a) substrate preparation, (b) selective exposure of substrate, (c) mask formation by differential solubility, (d) etching, (e) stripping of resist, (/) doping, (g) reoxidation of silicon surface, (h) formation of gate oxide, and (i) metal deposition and patterning. Abbreviations are defined as follows p-Si, p-type silicon PR, photoresist S, source G, gate and D, drain.

FIGURE 20.13 Metal gate transistors fabricated using CMP to enable exposure of the top of NMOS and PMOS gates (independently) followed by FUSI reaction of gates to form silicided metal gates (from Ref 12). 

A possible fabrication process flow for a single 90-nm technology node microprocessor CMOS inverter, consisting of two transistors— nMOS and pMOS—is presented in this section. Cross-sectional views of the inverter are provided for each major operation, with the operations involving lithographic masking called out with thicker lines, where possible. It must be noted that the illustration is for only a small microscopic area of a microprocessor that is one of hundreds of microprocessors that may populate a given 300-mm wafer at the end of the fabrication process. 

The twin-well process is typically the first step in CMOS wafer fabrication and is used to define the active regions of the nMOS and pMOS transistors. A twin well consists of a p-well and an n-well, with each well requiring some number of steps to fabricate. The twin-well process thus consists of two processes n-well formation and p-well formation. 

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