Total consumed silicon area of multiple-reticle wafer

Within the paradigm of 3-D integration, the input VLSI system is built into m device layers, each having an equal area of A/m. The yield of the 3-D implementation is the accumulative yield over all layers  

While the yield loss has to accumulate in the fabrication process, the Y 1 factor in the denominator suggests that the 3-D integration scheme is inherently more costly than the monolithic scheme. As a matter of fact, when the 3-D bonding step has an assembling yield of 95%, the total consumed silicon area of the 3-D implementation is 28.1 cm.  

Under the 2.5-D integration context, a VLSI system is partitioned into m parts and then each part is fabricated as a separated die on different wafers. Finally these dies are assembled on a common substrate. Again we assume that every die has the same area, Aim. 

As a result, the accumulative yield of one single die, F,.2.5-D, can be computed as the product of three components (1) Yt, which is the yield loss due to its own fabrication process (2) Foyers, the yield loss due to the assembling of other dies and (3) Fa, yield loss due to the final 3-D stacking process. 

F can be straightforwardly determined by Equation (2.5) and Fa can be presupposed to have a constant value of 0.95. The computation of Fothers depends on the fault coverage level of the dies (designated as Fc) in a 2.5-D system151  

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Figure 2.1 Total consumed silicon area of multiple-reticle wafer...

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