Memory address space buffer

The architecture described above is particularly well designed to achieve the complete isolation of the monitors from the monitored apphcation. Indeed, each monitor is an independent task which can be restricted to its own memory address space, interacting with the application only through the miidtrectional communication channels implemented by the event buffers. 

After the image has been successfully captured, the contents of the buffer memory may be mapped onto the address space of the Unibus of a PDP11/04 minicomputer for quantitive analysis, via a group of programs (SIM-1) (7). Approaches to analysis available to us include least squares fitting (5), eigen analysis (3). and... 

The Zoran 38000 has an internal data path of 20 bits as well as a 20 bit address bus. The two accumulators have 48 bits. It can perform a Dolby AC-3 [Vernon, 1995] five channel decoder in real time, although the memory space is also limited to one Megaword. It has a small (16 instruction) loop buffer as well as a single instruction repeat. The instruction set has support for block floating point as well as providing simultaneous add and subtract for FFT butterfly computation. 

To receive data from the Ethernet line, the host CPU sets aside an adequate amount of buffer space and invokes the co-processor by writing to a memory mapped address. The co-processor responds by requesting bus control, and then reading the command instruction from memory. Upon enabling the coprocessor in receive mode, the asynchronously arriving data frames are stored into a free memory area. Once an entire error-free frame is received, the coprocessor fetches the adress of the next free receive buffer and interrupts the CPU. Transmission of data is performed in a similar manner. 

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See also in sourсe #XX -- [ , ]

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