Loop statement

Executable statements affecting the order in which the program instructions are executed include conditional (branching) statements, iterative (looping) statements, and statements which call subprogram units. 

There are four kinds of loop statements in Verilog HDL. 

The for-loop statement is the one typically supported for synthesis. A for-loop is implemented by unrolling the for-loop, that is, all statements within the for-loop are replicated, once for each value of the for-loop index. This puts a restriction on the for-loop bounds, which must therefore evaluate to constants. Here is an example of a for-loop statement. 

After in-line expansion of the function call and further in-line expansion of the for-loop statement, the following code is obtained. 

Standard BASIC includes several loop constructs. The general loop eonstruct can have the exit condition attached to the DO statement, attached to the LOOP statement, or loeated somewhere in between. The following program fragment illustrates the middle exit from a DO loop ... 

The following subsections give the semantics for three kinds of statement wait scheduled assignment, and their sequential and parallel compositions. A process consists of a looped statement with at least one wait statement inside the loop. Parallelism is only one level deep in VHDL and in VHDL-AMS. 

We now consider a structure node in which the set of nodes is partitioned in a number of subsets. Nodes in a subset have identical behavior. These subsets are called node domains. Let D be a domain and iV be a type of node. Then a node domain V)vd is characterized by the pair (iV, D) and consists of an indexed set of nodes Vnd = i I D. The node domain of the Floyd-Steinberg algorithm is given in figure 5. The boundary planes of the domain are derived from the upper and lower bound expressions of the FOR-loop statements of its nested loop program. 

To insert a/or loop, type the name of the variable, use a definition equals sign, then select Add Line on the Programming toolbar, and choose for. For loops will continue to execute a line of code for a given range variable therefore, as a minimum, a range variable and a loop statement are required. A simple example is shown as follows ... 

A For-Loop statement enables a set of other sequential statements to be repeated for a fixed number of iterations. It has the following syntax. 

By acting on the present value of the iteration parameter or any other condition, fee present iteration of the loop or the whole For Loop statement can be terminated. See Box 6.12... 

An Exit statement must be used inside an Infinite Loop statement... 

The description of the multiplier is compact because of the Loop statement. Of course the designer must always be aware of the amotmt of hardware diat can be produced when this is s3mthesized. The same applies to arithmetic operators. 

This chapter has demonstrated how VHDL can be applied in die design of datapath logic in particular, adder and multiplier drcuits. The relational and arithmetic operators that are built in to the language shotdd always be used with care because of the amount of hardware that they can produce, espedally when used inside Loop statements ... 

Remember that multiple calls to the same procedure will result in logic being generated each time. For a concurrent procedure, multiple calls can be made through a For-Generate statement. For a sequential procedure, multiple calls can be made with a For-Loop statement. 

There are four looping statements in VBA (For...Next, Do While...Loop, Do...Loop While, For Each...Next). Only the first two of these are presented since the other two are repetitious (or can be confusing). 

This looping statement executes a series of statements as long as a given condition is True. The syntax of this statement is... 

---