Lateral epitaxial growth

FIGURE 20.16 In a second 3D fabrication scheme, CMP is used to smooth the wafer surface after lateral epitaxial growth. After a first layer of transistor fabrication, a second layer of device quality Si is grown from seed holes in Si02 down to the original wafer surface. This process allows for transistor fabrication on multiple levels of the wafer surface (from Ref. 15). 

Figure 5.8 Cross-sectional TEM images of GaN films on (a) nonporous SiC substrate, and (b)-(d) on porous SiC substrates. The label ps denotes a porous substrate and np denotes a nonporous substrate. The surface pore density of the substrate in (b) is 13 prrr2, and in (c) and (d) is 11.5 pm-2. The open tubes in the GaN films on porous substrates are marked by T (the tubes appear white in contrast near the top of the film where they are empty, and black near the interface where they are filled by Ga). The regions labeled D contain a relatively low number of threading dislocations originating at the interface (due to the lateral epitaxial growth over the substrate pores), and they contain dislocation half-loops gliding in from tubes. One half-loop is faintly seen to the right of a in (c). Reproduced from A. Sagar et al., J. Vac. Sci. Technol. B 21, 1812. Copyright (2003), with permission from the American Institute of Physics...

Figure 5.9 Magnified images of GaN on porous 6H-SiC. The half-loops are clearly seen in (a), with some of them indicated by arrows. The region marked by D in (b) shows nearly defect-free GaN due to the lateral epitaxial growth over the pores. The open tubes are marked by T ...

GaN Lateral Epitaxy Growth Using Porous SiNx, TiNx and SiC... 

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