Interconnect Delay Impact on Performance

The interconnect delay in an IC is due to the capacitance (C) and resistance (R) associated with the metal lines. The most widely used measure of the interconnect delay is the RC time delay, which is the time it takes for the voltage at one end of a metal line to reach 63% of its final value when a step input is presented at the other end of the line. The RC time delay is equal to the product of the total resistance and the total capacitance of the line. The resistance of the line is given by  

To reduce the RC time delay, p, e, and 1 must be decreased, while d and t must be increased. 

Equation 2.3 suggests that the RC delay is not dependent upon line width and therefore should not change as line dimensions are decreased. However, often when feature sizes are scaled on an IC, the line thickness and the ILD thickness are scaled down but, as a result of increasing chip complexity, the line length remains constant. As a result, the RC delay does increase as dimensions are scaled. 

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