High-level data-path mapping

the basic arithmetic, logic, and relational operations in the application are mapped to a set of dedicated ASUs. This is done in four basic synthesis steps in the script [18, 3, 8]. 

operations are grouped into clusters in order to exploit the structure present in the flow graph. The objective function is cluster similarity within the timing constraints imposed. Within the single clock cycle constraint, which 

In order to evaluate the quality and feasibility of this allocation and assignment, two more subtasks are performed. These provide important feedback to the designer, and they can initiate design iterations  

For the YUV-RGB demonstrator, it is possible to schedule the 12 available clusters on the three ASUs within the four available clock cycles. This means a functional hardware use of 100%. This is feasible by using an ILP-based scheduling technique, which can deal with very tight schedules in a close-to-optimal way. This is in contrast with the scheduling techniques for the highly multiplexed processors in chapters 8 and 9. 

The final ASU architecture has very little programmability overhead and is optimal for the given throughput requirement and the available library of hardware operators. Subsequent design stages are needed in Cathedral to arrive at the actual layout [8], 

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The differences between the high-level data path mapping stage for Cathedral-2nd and Cathedral-3 are as follows ... 

High-level data-path mapping In order to allocate operators in the data path, all operations of the DSFG were analysed. Besides the type of operation also the dimensions of operands and results are important. Prom this the required operator types, as well as their minimal dimensions can be deducted. The operator dimensions determine whether single or multiple precision arithmetic should be used. 

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