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Hierarchical control supervisory layer

Practical considerations in implementing the hierarchical control framework developed above concern the availability of manipulated inputs to address the control objectives in the slow time scale (it is possible that dim(us) < dim(ys)), as well as achieving a tighter coordination between the distributed and supervisory control layers. Both issues are effectively addressed by using a cascaded control configuration, which extends the choice of controlled variables in the slow time scale to include the setpoints y)p of the distributed controllers. [Pg.44]

Figure 3.4 Hierarchical control relies on separate, but coordinated, fast and slow controllers, designed on the basis of the respective reduced-order models, to compute the values of the separate inputs that influence the fast and slow dynamics of the process. Tighter coordination between the distributed and supervisory control layers is achieved by using a cascaded configuration. Figure 3.4 Hierarchical control relies on separate, but coordinated, fast and slow controllers, designed on the basis of the respective reduced-order models, to compute the values of the separate inputs that influence the fast and slow dynamics of the process. Tighter coordination between the distributed and supervisory control layers is achieved by using a cascaded configuration.
The resulting hierarchical control structure is represented schematically in Figure 5.2. Note that, while controller design proceeds in a bottom-up manner, starting from the fastest time scale, during the operation of the process there will exist a tight top-down interconnection via control cascades between the supervisory and regulatory layers. [Pg.111]

The design of the integration architecture used in the test platform described in Section 6 follows the CIM hierarchical structure that contemplates three main levels of aggregation planning and scheduling at the upper level, co-ordination at the intermediate level and supervisory control at the lowest level. This three layered architecture is represented in Fig. 10. [Pg.521]


See also in sourсe #XX -- [ Pg.43 ]




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