HDL Design Wizard and Language Assistant

HDL Design Wizard is a GUI tool to help the designers visually declare the interfaces of an HDL module (in Verilog) and entity (in VHDL). Input, output or bidirectional ports are defined. 

T0 change attributes of a port, select it on the list. Then you can change its name, range and direction to set other attributes click Advanced. 

T0 delete a port select it on the list and click Delete. 

For a registered I/O port, click on the Advanced... button to specify. 

After entering all the I/O ports, you should see a Verilog interface file similar to the following. Note that mac vl is used as both the module name and file name which is not necessary, be convenient and helpful. In practice, the file name has no relationship with the module name. 

---